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Biometric fingerprint solution : Orway.com ( part 2)

BloggausPreviously we wrote about some of our engineers’ experience with biometrics and in particular how they worked on implementation and testing of various parts of the fingerprint feature extraction and matching algorithms developed by Orway, a disruptive Italian startup.

A fingerprint feature extraction algorithm typically involves multiple stages of processing that follow one another. The number of points that must be processed is typically large and the mathematical operations that would normally be used are relatively slow. And there are usually performance requirements that must be met: no one would be happy if scanning their fingerprint took more than a second or so. For that reason optimization plays an important role in software

development in biometrics.

Sisucode engineers approached the task of optimization on several levels. Firstly, there is always a possibility to perform some optimization at the algorithmic level. Your first-pass-proof-of-concept algorithm can usually be re-written producing a faster equivalent. This was typically done in tandem with the scientists at Orway to ensure that the resulting math was right.

Tricks like offline calculations, look-up tables, caching, etc. were implemented where it made sense.

Then there are the optimizations performed by the compiler itself – those were made use of by choosing appropriate compilation options and using various compiler intrinsics (such as SIMD, etc.) in the source code.

The nature of feature extraction is such that most operations can benefit massively from parallel processing as you typically go over a fingerprint’s data set with a certain stride and you look at points and their neighborhoods and do some processing with them and in most cases you can do so on multiple cores or threads – something we took full advantage of in our implementation and produced a resulting code that ran much faster.

We see further potential gains in performance in the use of specialized hardware built on FPGAs and it would be an interesting challenge for Sisucode engineers to take on.

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